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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12xxx-1E
8-bit Microcontrollers
CMOS
F2MC-8FX MB95430H Series
MB95F432H/F433H/F434H MB95F432K/F433K/F434K
DESCRIPTION
MB95430H is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral resources. Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FEATURES
* F2MC-8FX CPU core Instruction set optimized for controllers * Multiplication and division instructions * 16-bit arithmetic operations * Bit test branch instructions * Bit manipulation instructions, etc. * Clock * Selectable main clock source Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz) External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz) Main CR clock (1/8/10/12.5 MHz 2%, maximum machine clock frequency: 12.5 MHz) * Selectable subclock source Sub-OSC clock (32.768 kHz) External clock (32.768 kHz) Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz) * Timer * 8/16-bit composite timer x 1 channel * 16-bit PPG x 1 channel * 16-bit free-running timer x 1 channel * 16-bit output compare x 2 channels * Time-base timer x 1 channel * Watch prescaler x 1 channel * UART/SIO x 1 channel * Full duplex double buffer * Capable of clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data transfer (Continued)
For the information for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
Copyright(c)2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2010.8
MB95430H Series
(Continued) * I2C x 1 channel * Built-in wake-up function * Voltage comparator x 4 channels * Operational amplifier (OPAMP) x 1 channel * Software-select programmable gain * Software-select standalone option * Power down function included * External interrupt x 8 channels * Interrupt by edge detection (rising edge, falling edge, and both edges can be selected) * Can be used to wake up the device from different low power consumption (standby) modes * 8/10-bit A/D converter x 17 channels * 8-bit and 10-bit resolution can be chosen. * Low power consumption (standby) modes * Stop mode * Sleep mode * Watch mode * Time-base timer mode * I/O port * MB95F432H/F433H/F434H (maximum no. of I/O ports: 28) General-purpose I/O ports (N-ch open drain) :1 General-purpose I/O ports (CMOS I/O) : 27 * MB95F432K/F433K/F434K (maximum no. of I/O ports: 29) General-purpose I/O ports (N-ch open drain) :2 General-purpose I/O ports (CMOS I/O) : 27 * On-chip debug * 1-wire serial control * Serial writing supported (asynchronous mode) * Hardware/software watchdog timer * Built-in hardware watchdog timer * Built-in software watchdog timer * Low-voltage detection reset circuit * Built-in low-voltage detector * Clock supervisor counter * Built-in clock supervisor counter function * Programmable port input voltage level * CMOS input level / hysteresis input level * Dual operation Flash memory * The erase/write operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. * Flash memory security function * Protects the content of the Flash memory
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PRODUCT LINE-UP
Part number MB95F432H Parameter MB95F433H MB95F434H MB95F432K MB95F433K MB95F434K
Type Flash memory product Clock supervisor It supervises the main clock oscillation. counter Program ROM 8 Kbyte 12 Kbyte 20 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte capacity RAM capacity 240 bytes 240 bytes 496 bytes 240 bytes 240 bytes 496 bytes Low-voltage No Yes detection reset Reset input Dedicated Selected by software Number of basic instructions : 136 Instruction bit length : 8 bits Instruction length : 1 to 3 bytes CPU functions Data bit length : 1, 8 and 16 bits Minimum instruction execution time : 61.5 ns (with machine clock = 16.25 MHz) Interrupt processing time : 0.6 s (with machine clock = 16.25 MHz) I/O ports (Max): 29 I/O ports (Max): 28 GeneralCMOS I/O: 27 CMOS I/O: 27 purpose I/O N-ch open drain: 1 N-ch open drain: 2 Time-base Interrupt cycle: 0.256 ms to 8.3 s (when external clock = 4 MHz) timer Hardware/ Reset generation cycle software - Main oscillation clock at 10 MHz: 105 ms (Min) watchdog timer The sub-CR clock can be used as the source clock of the hardware watchdog timer. Wild register It can be used to replace three bytes of data. 17 channels (Ch. 16 is the channel for OPAMP output.) 8/10-bit A/D converter 8-bit resolution and 10-bit resolution can be chosen. 1 channel 8/16-bit The timer can be configured as an "8-bit timer x 2 channels" or a "16-bit timer x 1 channel". composite It has built-in timer function, PWC function, PWM function and input capture function. timer Count clock: it can be selected from internal clocks (seven types) and external clocks. It can output square wave. 8 channels External Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.) interrupt It can be used to wake up the device from different standby modes. 1-wire serial control On-chip debug It supports serial writing. (asynchronous mode) 1 channel Data transfer with UART/SIO is enabled. It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate generator and an error detection function. UART/SIO It uses the NRZ type transfer format. LSB-first data transfer and MSB-first data transfer are available to use. Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data transfer is enabled. (Continued)
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(Continued)
Part number MB95F432H Parameter MB95F433H MB95F434H MB95F432K MB95F433K MB95F434K
I2C
16-bit PPG Output compare Voltage comparator
1 channel Master/slave transmission and receiving It has a bus error function, an arbitration function, a transmission direction detection function and a wake-up function. It also has functions of generating and detecting repeated START conditions. PWM mode and single-shot mode are available to use. Ch. 0 can work with the multi-functional timer or individually. 1 channel of 16-bit free-running timer with a compare buffer 2 channels of 16-bit output compare 4 channels This is an operational amplifier used in an induction heater. It contains 7 software (registers) select close loop gain selections for ground current sensing according to different sense resistor values. The OPAMP can also work as a standalone OPAMP. It selects closed loop gain for ground current sensing according to different sense resistor values of a standalone OPAMP. Eight different time intervals can be selected.
OPAMP
Watch prescaler
It supports automatic programming, Embedded Algorithm, and write/erase/erase-suspend/ erase-resume commands. It has a flag indicating the completion of the operation of Embedded Algorithm. Flash memory Number of write/erase cycles: 100000 Data retention time: 20 years Flash security feature for protecting the content of the Flash memory Standby mode Sleep mode, stop mode, watch mode, time-base timer mode FPT-32P-M30 Package DIP-32P-M06
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PACKAGES AND CORRESPONDING PRODUCTS
Part number MB95F432H Package FPT-32P-M30 DIP-32P-M06 O O O O O O O O O O O O MB95F433H MB95F434H MB95F432K MB95F433K MB95F434K
O: Available
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MB95430H Series
DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
* Current consumption When using the on-chip debug function, take account of the current consumption of flash erase/write. For details of current consumption, see " ELECTRICAL CHARACTERISTICS". * Package For details of information on each package, see " PACKAGES AND CORRESPONDING PRODUCTS" and " PACKAGE DIMENSIONS". * Operating voltage The operating voltage varies, depending on whether the on-chip debug function is used or not. For details of the operating voltage, see " ELECTRICAL CHARACTERISTICS". * On-chip debug function The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool.
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PIN ASSIGNMENT
Vss PF1/X1 PF0/X0 PF2/RST P67/CMP3_N/AN15 P66/CMP3_P/AN14 P65/CMP3_O/UO/SDA P64/CMP2_N/AN13 PG2/PPG0/X1A/OUT1 PG1/TRG/ADTG/X0A/BZ/OUT0 Vcc C P60/OPAMP_P P61/OPAMP_N P62/OPAMP_O P12/EC0/UI/SCL/DBG 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8
(TOP VIEW) LQFP32 FPT-32P-M30
24 23 22 21 20 19 18 17
P63/CMP2_P/AN12 P76/CMP2_O/UCK P75/CMP1_N/AN11 P74/CMP1_P/AN10 P73/CMP1_O/OUT1/PPG P72/CMP0_N/AN09 P71/CMP0_P/AN08 P70/CMP0_O/OUT0/TRG
9 10 11 12
13 14 15 P04/INT04/AN04/UI/SCL P05/INT05/AN05/TO0 P06/INT06/AN06/TO1
P00/INT00/AN00 P01/INT01/AN01/BZ P02/INT02/AN02/UCK P03/INT03/AN03/UO/SDA
P07/INT07/AN07/EC0
16
PF2/RST PF0/X0 PF1/X1 Vss PG2/PPG0/X1A/OUT1 PG1/TRG/ADTG/X0A/BZ/OUT0 Vcc C P60/OPAMP_P P61/OPAMP_N P62/OPAMP_O P12/EC0/UI/SCL/DBG P00/INT00/AN00 P01/INT01/AN01/BZ P02/INT02/AN02/UCK P03/INT03/AN03/UO/SDA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29
P67/CMP3_N/AN15 P66/CMP3_P/AN14 P65/CMP3_O/UO/SDA P64/CMP2_N/AN13 P63/CMP2_P/AN12 P76/CMP2_O/UCK P75/CMP1_N/AN11 P74/CMP1_P/AN10 P73/CMP1_O/OUT1/PPG P72/CMP0_N/AN09 P71/CMP0_P/AN08 P70/CMP0_O/OUT0/TRG P07/INT07/AN07/EC0 P06/INT06/AN06/TO1 P05/INT05/AN05/TO0 P04/INT04/AN04/UI/SCL
(TOP VIEW) SH-DIP32 DIP-32P-M06
28 27 26 25 24 23 22 21 20 19 18 17
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MB95430H Series
PIN DESCRIPTION
Pin no. LQFP32*1 SH-DIP32*2 Pin name PG2 1 5 PPG X1A OUT1 PG1 TRG 2 6 ADTG X0A BZ OUT0 3 4 5 6 7 7 8 9 10 11 VCC C P60 OPAMP_P P61 OPAMP_N P62 OPAMP_O P12 EC0 8 12 UI SCL DBG P00 9 13 INT00 AN00 P01 10 14 INT01 AN01 BZ P02 11 15 INT02 AN02 UCK E E E H -- -- K K J C C I/O circuit type*3 16-bit PPG output pin Subclock I/O oscillation pin Output compare ch. 1 output pin General-purpose I/O port 16-bit PPG trigger input pin A/D converter trigger input pin Subclock I/O oscillation pin Buzzer output pin Output compare ch. 0 output pin Power supply pin Capacitor connection pin General-purpose I/O port Operational amplifier input pin General-purpose I/O port Operational amplifier input pin General-purpose I/O port Operational amplifier output pin General-purpose I/O port 8/16-bit composite timer external clock input pin UART/SIO data input pin I2C clock I/O pin DBG input pin General-purpose I/O port External interrupt input pin A/D converter analog input pin General-purpose I/O port External interrupt input pin A/D converter analog input pin Buzzer output pin General-purpose I/O port External interrupt input pin A/D converter analog input pin UART/SIO clock I/O pin (Continued) Function General-purpose I/O port
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Pin no. LQFP32*1 SH-DIP32*2 Pin name P03 INT03 12 16 AN03 UO SDA P04 INT04 13 17 AN04 UI SCL P05 14 18 INT05 AN05 TO0 P06 15 19 INT06 AN06 TO1 P07 16 20 INT07 AN07 EC0 P70 17 21 CMP0_O OUT0 TRG P71 18 22 CMP0_P AN08 P72 19 23 CMP0_N AN09 P73 20 24 CMP1_O OUT1 PPG D I I D E E E F F I/O circuit type*3
Function General-purpose I/O port External interrupt input pin A/D converter analog input pin UART/SIO data output pin I2C data I/O pin General-purpose I/O port External interrupt input pin A/D converter analog input pin UART/SIO data input pin I2C clock I/O pin General-purpose I/O port External interrupt input pin A/D converter analog input pin Timer output pin General-purpose I/O port External interrupt input pin A/D converter analog input pin Timer output pin General-purpose I/O port External interrupt input pin A/D converter analog input pin 8/16-bit composite timer external clock input pin General-purpose I/O port Comparator ch. 0 output pin Output compare ch. 0 output pin 16-bit PPG trigger input pin General-purpose I/O port Comparator ch. 0 positive input pin A/D converter analog input pin General-purpose I/O port Comparator ch. 0 negative input pin A/D converter analog input pin General-purpose I/O port Comparator ch. 1 output pin Output compare ch. 1 output pin 16-bit PPG output pin (Continued)
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MB95430H Series
(Continued) Pin no. LQFP32*1 SH-DIP32*2 Pin name P74 21 25 CMP1_P AN10 P75 22 26 CMP1_N AN11 P76 23 27 CMP2_O UCK P63 24 28 CMP2_P AN12 P64 25 29 CMP2_N AN13 P65 26 30 CMP3_O UO SDA P66 27 31 CMP3_P AN14 P67 28 32 CMP3_N AN15 PF2 29 1 RST PF0 X0 PF1 X1 VSS A I I L I I D I I
I/O circuit type*3
Function General-purpose I/O port Comparator ch. 1 positive input pin A/D converter analog input pin General-purpose I/O port Comparator ch. 1 negative input pin A/D converter analog input pin General-purpose I/O port Comparator ch. 2 output pin UART/SIO clock I/O pin General-purpose I/O port Comparator ch. 2 positive input pin A/D converter analog input pin General-purpose I/O port Comparator ch. 2 negative input pin A/D converter analog input pin General-purpose I/O port Comparator ch. 3 output pin UART/SIO data output pin I2C data I/O pin General-purpose I/O port Comparator ch. 3 positive input pin A/D converter analog input pin General-purpose I/O port Comparator ch. 3 negative input pin A/D converter analog input pin General-purpose I/O port Reset pin Dedicated reset pin in MB95F432H/F433H/F434H General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock I/O oscillation pin Power supply pin (GND)
30 31 32
2 3 4
B B --
*1: Package code: FPT-32P-M30 *2: Package code: DIP-32P-M06 *3: For the I/O circuit types, see " I/O CIRCUIT TYPE".
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I/O CIRCUIT TYPE
Type A Circuit
Reset input / Hysteresis input Reset output / Digital output N-ch
Remarks * N-ch open drain output * Hysteresis input * Reset output * Oscillation circuit * High-speed side Feedback resistance: approx. 1 M * CMOS output * Hysteresis input
B
P-ch
Port select Digital output
N-ch
Digital output Standby control Hysteresis input Clock input
X1
X0 Standby control / Port select
P-ch
Port select Digital output
N-ch
Digital output Standby control Hysteresis input
C
R P-ch P-ch N-ch
Port select Pull-up control Digital output Digital output Standby control Hysteresis input Clock input X1A
* Oscillation circuit * Low-speed side Feedback resistance: approx.10 M * CMOS output * Hysteresis input * Pull-up control available
X0A Standby control / Port select Port select
R
Pull-up control Digital output Digital output
N-ch
P-ch
Digital output Standby control Hysteresis input
(Continued)
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MB95430H Series
Type D
P-ch Digital output Digital output N-ch Standby control Hysteresis input
Circuit
Remarks * CMOS output * Hysteresis input
E
R P-ch P-ch N-ch
Pull-up control
Digital output Digital output
* * * *
CMOS output Hysteresis input Pull-up control available Analog input
Analog input A/D control Standby control Hysteresis input
F
R P-ch P-ch N-ch
Pull-up control I2C output control Digital output Digital output
* * * * * *
CMOS output Hysteresis input CMOS input Pull-up control available Analog input N-ch open drain output (as I2C output)
Analog input A/D control Standby control Hysteresis input CMOS input
G
R P-ch P-ch N-ch
Pull-up control
* CMOS output * Hysteresis input * Pull-up control available
Digital output Digital output Standby control Hysteresis input
H
Standby control Hysteresis input CMOS input Digital output N-ch
* N-ch open drain output * Hysteresis input * CMOS input
(Continued)
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(Continued) Type I
P-ch N-ch Analog input for A/D Analog input for VC Analog input control Standby control Hysteresis input P-ch
Circuit
Digital output Digital output
Remarks * CMOS output * Hysteresis input
J
P-ch
P-ch
Digital output Digital output
* CMOS output * Hysteresis input
N-ch Analog output Analog output control Standby control Hysteresis input
K
P-ch
P-ch
Digital output Digital output
* CMOS output * Hysteresis input
N-ch Analog input Analog input control Standby control Hysteresis input
L
P-ch
P-ch
I2C output control Digital output Digital output
N-ch Standby control Hysteresis input CMOS input
* * * *
CMOS output Hysteresis input CMOS input N-ch open drain output (as I2C output)
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MB95430H Series
NOTES ON DEVICE HANDLING
* Preventing latch-ups When using the device, ensure that the voltage applied does not exceed the maximum voltage rating. In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in "1. Absolute Maximum Ratings" of " ELECTRICAL CHARACTERISTICS" is applied to the VCC pin or the VSS pin, a latch-up may occur. When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. * Stabilizing supply voltage Supply voltage must be stabilized. A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply. * Notes on using the external clock When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode.
PIN CONNECTION
* Treatment of unused pins If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 k. Set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it unconnected. * Power supply pins To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance. It is also advisable to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between the VCC pin and the VSS pin at a location close to this device. * DBG pin Connect the DBG pin directly to an external pull-up resistor. To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board. The DBG pin should not stay at "L" level after power-on until the reset output is released. * RST pin Connect the RST pin directly to an external pull-up resistor. To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board. The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output of the RST/PF2 pin can be enabled by the RSTOE bit in the SYSC1 register, and the reset input function and the general purpose I/O function can be selected by the RSTEN bit in the SYSC1 register.
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* C pin Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. * DBG/RST/C pins connection diagram
DBG C RST Cs
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MB95430H Series
BLOCK DIAGRAM
F2MC-8FX CPU
PF2*1/RST*2 PF1/X1*2 PF0/X0*2 (PG2/X1A*2) (PG1/X0A*2)
Reset with LVD
Flash with security function (20 Kbyte)
Oscillator circuit
CR oscillator
RAM (496 bytes) P72/CMP0_N P71/CMP0_P P70/CMP0_O trigger 16-bit PPG stop
Comparator ch. 0 Clock control
(P12*1/DBG)
On-chip debug Wild register
PG2/PPG, (P73/PPG) PG1/TRG, (P70/TRG)
(P00/INT00 to P07/INT07)
8
8
External interrupt Interrupt controller Comparator ch. 1
P73/CMP1_O P74/CMP1_P P75/CMP1_N
(P05/TO0) (P06/TO1) P12*1/EC0, (P07/EC0) (P01/BZ, PG1/BZ) 2 2 8/16-bit composite timer OPAMP
P60/OPAMP_P P61/OPAMP_N
Buzzer 16-bit free-run timer
Internal bus
P62/OPAMP_O (PG1/ATDG)
P00/AN00 P01/AN01 P02/AN02 P03/AN03 P04/AN04
(P70/OUT0, PG1/OUT0) (P73/OUT1, PG2/OUT1) P67/CMP3_N P66/CMP3_P P65/CMP3_O
16-bit output compare
Comparator ch. 3 8/10-bit A/D converter
P05/AN05 P06/AN06 P07/AN07 (P71/AN08) (P72/AN09) (P73/AN10) (P74/AN11) (P75/AN12)
P64/CMP2_N P63/CMP2_P P76/CMP2_O (P02/UCK, P76/UCK) (P03/UO, P65/UO) (P04/UI, P12*1/UI) UART/SIO Comparator ch. 2
(P63/AN13) (P64/AN14) (P65/AN15) (P04/SCL*3, P12*1/SCL) (P03/SDA*3, P65/SDA*3)
I2 C
Port Vcc Vss C *1: PF2 and P12 are N-ch open drain pins. *2: Software option
Port
*3: This pin will work as an N-ch open drain pin during I2C operation. Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
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CPU CORE
* Memory Space The memory space of the MB95430H Series is 64 Kbyte in size, and consists of an I/O area, a data area, and a program area. The memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. The memory maps of the MB95430H Series are shown below. * Memory Maps
MB95F432H/F432K
0000H I/O 0080H 0090H 0100H 0180H Access prohibited 0F80H Extended I/O 1000H Access prohibited B000H C000H Flash 4 Kbyte B000H C000H 1000H Access prohibited Flash 4 Kbyte Access prohibited E000H Flash 8 Kbyte FFFFH FFFFH B000H 0F80H Extended I/O 1000H Access prohibited Access prohibited RAM 240 bytes Register 0180H Access prohibited Access prohibited 0F80H Extended I/O 0080H 0090H 0100H 0000H I/O Access prohibited RAM 240 bytes Register 0200H 0280H 0080H 0090H 0100H
MB95F433H/F433K
0000H
MB95F434H/F434K
I/O Access prohibited RAM 496 bytes Register
Access prohibited F000H FFFFH
Flash 20 Kbyte
Flash 4 Kbyte
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MB95430H Series
I/O MAP
Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH to 0015H 0016H 0017H 0018H 0019H 0020H to 0027H 0028H 0029H 002AH 002BH 002CH 002DH to 0034H 0035H 0036H 0037H 0038H 0039H Register abbreviation PDR0 DDR0 PDR1 DDR1 -- WATR -- SYCC STBC RSRR TBTC WPCR WDTC SYCC2 -- PDR6 DDR6 PDR7 DDR7 -- PDRF DDRF PDRG DDRG PUL0 -- PULG T01CR1 T00CR1 BUZZ -- Port G pull-up register 8/16-bit composite timer 01 status control register 1 ch. 0 8/16-bit composite timer 00 status control register 1 ch. 0 Buzzer control register (Disabled) Port F data register Port F direction register Port G data register Port G direction register Port 0 pull-up register (Disabled) Port 6 data register Port 6 direction register Port 7 data register Port 7 direction register (Disabled) Standby control register Reset source register Time-base timer control register Watch prescaler control register Watchdog timer control register System clock control register 2 (Disabled) Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register (Disabled) System clock control register Register name R/W Initial value R/W R/W R/W R/W -- R/W -- R/W R/W R/W R/W R/W R/W -- R/W R/W R/W R/W -- R/W R/W R/W R/W R/W -- R/W R/W R/W R/W -- 00000000B 00000000B 00000000B 00000000B -- 11111111B -- 0000X011B 00000XXXB 00000000B 00000000B 00XX0000B XX100011B -- 00000000B 00000000B 00000000B 00000000B -- 00000000B 00000000B 00000000B 00000000B 00000000B -- 00000000B 00000000B 00000000B 00000000B -- (Continued)
R/W XXXXXXXXB
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Register abbreviation CMR0 CMR1 CMR2 CMR3 OPCR -- PCNTH0 PCNTL0 PTGS0 -- OCUOC -- EIC00 EIC10 EIC20 EIC30 -- SYSC2 -- IBCR00 IBCR10 IBSR0 IDDR0 IAAR0 ICCR0 SMC10 SMC20 SSR0 TDR0 RDR0 -- TCDTH TCDTL CPCLRH CPCLRL I2C bus control register 0 I C bus control register 1 I C bus status register I2C data register I2C address register I C clock control register UART/SIO serial mode control register 1 ch. 0 UART/SIO serial mode control register 2 ch. 0 UART/SIO serial status and data register ch. 0 UART/SIO serial output data register ch. 0 UART/SIO serial input data register ch. 0 (Disabled) 16-bit free-running timer data register (upper) 16-bit free-running timer data register (lower) 16-bit free-running timer compare clear register (upper) 16-bit free-running timer compare clear register (lower)
2 2 2
Address 003AH 003BH 003CH 003DH 003EH 003FH to 0041H 0042H 0043H 0044H 0045H 0046H 0047H 0048H 0049H 004AH 004BH 004CH, 004DH 004EH 004FH 0050H 0051H 0052H 0053H 0054H 0055H 0056H 0057H 0058H 0059H 005AH 005BH 005CH 005DH 005EH 005FH
Register name Voltage comparator control register ch. 0 Voltage comparator control register ch. 1 Voltage comparator control register ch. 2 Voltage comparator control register ch. 3 OPAMP control register (Disabled) 16-bit PPG status control register upper ch. 0 16-bit PPG status control register lower ch. 0 16-bit PPG trigger source control register ch. 0 (Disabled) 16-bit output compare stop trigger control register (Disabled) External interrupt circuit control register ch. 0/ch. 1 External interrupt circuit control register ch. 2/ch. 3 External interrupt circuit control register ch. 4/ch. 5 External interrupt circuit control register ch. 6/ch. 7 (Disabled) System control register 2 (Disabled)
R/W Initial value R/W R/W R/W R/W R/W -- R/W R/W R/W -- R/W -- R/W R/W R/W R/W -- R/W -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R -- R/W R/W R R 000X0001B 000X0001B 000X0001B 000X0001B 00000011B -- 00000000B 00000000B 00000000B -- 00000000B -- 00000000B 00000000B 00000000B 00000000B -- 00000000B -- 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00100000B 00000001B 00000000B 00000000B -- 00000000B 00000000B 11111111B 11111111B (Continued)
DS07-12xxx-1E
19
MB95430H Series
Register abbreviation TCCSH TCCSL ETCCSH ETCCSL OCCP0H OCCP0L OCCP1H OCCP1L OCSH OCSL OCMCR EOCS ADC1 ADC2 ADDH ADDL -- FSR2 FSR SWRE0 FSR3 -- WREN WROR -- ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 --
Address 0060H 0061H 0062H 0063H 0064H 0065H 0066H 0067H 0068H 0069H 006AH 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH to 0F7FH
Register name 16-bit free-running timer control status register (upper) 16-bit free-running timer control status register (lower) 16-bit free-running timer extended control status register (upper) 16-bit free-running timer extended control status register (lower) 16-bit output compare channel 0 register (upper) 16-bit output compare channel 0 register (lower) 16-bit output compare channel 1 register (upper) 16-bit output compare channel 1 register (lower) 16-bit output compare control status register (upper) 16-bit output compare control status register (lower) 16-bit output compare mode control register 16-bit output compare extended control status register 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (upper) 8/10-bit A/D converter data register (lower) (Disabled) Flash memory status register 2 Flash memory status register Flash memory sector write control register 0 Flash memory status register 3 (Disabled) Wild register address compare enable register Wild register data test setting register (Disabled) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled)
R/W Initial value R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W R/W R -- R/W R/W -- R/W R/W R/W R/W R/W R/W -- 01000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B -- 00000000B 000X0000B 00000000B 0000XXXXB -- 00000000B 00000000B -- 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B -- (Continued)
20
DS07-12xxx-1E
MB95430H Series
Register abbreviation WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 WRARH3 WRARL3 WRDR3 -- T01CR0 T00CR0 T01DR T00DR TMCR0 -- PDCRH0 PDCRL0 PCSRH0 PCSRL0 PDUTH0 PDUTL0 -- PSSR0 BRSR0 -- AIDRH AIDRL --
Address 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H 0F8AH 0F8BH 0F8CH to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H to 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H to 0FBDH 0FBEH 0FBFH 0FC0H, 0FC1H 0FC2H 0FC3H 0FC4H to 0FE3H
Register name Wild register address setting register (upper) ch. 0 Wild register address setting register (lower) ch. 0 Wild register data setting register ch. 0 Wild register address setting register (upper) ch. 1 Wild register address setting register (lower) ch. 1 Wild register data setting register ch. 1 Wild register address setting register (upper) ch. 2 Wild register address setting register (lower) ch. 2 Wild register data setting register ch. 2 Wild register address setting register (upper) ch. 3 Wild register address setting register (lower) ch. 3 Wild register data setting register ch. 3 (Disabled) 8/16-bit composite timer 01 status control register 0 ch. 0 8/16-bit composite timer 00 status control register 0 ch. 0 8/16-bit composite timer 01 data register ch. 0 8/16-bit composite timer 00 data register ch. 0 8/16-bit composite timer 00/01 timer mode control register ch. 0 (Disabled) 16-bit PPG down counter register (upper) ch. 0 16-bit PPG down counter register (lower) ch. 0 16-bit PPG cycle setting buffer register (upper) ch. 0 16-bit PPG cycle setting buffer register (lower) ch. 0 16-bit PPG duty setting buffer register (upper) ch. 0 16-bit PPG duty setting buffer register (lower) ch. 0 (Disabled) UART/SIO prescaler select register ch. 0 UART/SIO baud rate setting register ch. 0 (Disabled) A/D input disable register (upper) A/D input disable register (lower) (Disabled)
R/W Initial value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W -- R/W R/W R/W R/W R/W R/W -- R/W R/W -- R/W R/W -- 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B -- 00000000B 00000000B 00000000B 00000000B 00000000B -- 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B -- 00000000B 00000000B -- 00000000B 00000000B -- (Continued)
DS07-12xxx-1E
21
MB95430H Series
(Continued) Address 0FE4H 0FE5H 0FE6H, 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH 0FEEH 0FEFH 0FF0H to 0FFFH Register abbreviation CRTH CRTL -- SYSC1 CMCR CMDR WDTH WDTL -- ILSR WICR -- Input level select register Interrupt pin control register (Disabled) Register name Main CR clock trimming register (upper) Main CR clock trimming register (lower) (Disabled) System configuration register 1 Clock monitoring control register Clock monitoring data register Watchdog timer selection ID register (upper) Watchdog timer selection ID register (lower) (Disabled) R/W Initial value R/W 0XXXXXXXB R/W 00XXXXXXB -- R/W R/W R R R -- R/W R/W -- -- 11000011B 00000000B 00000000B XXXXXXXXB XXXXXXXXB -- 00000000B 01000000B --
* R/W access symbols R/W : Readable / Writable R : Read only W : Write only * Initial value symbols 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is indeterminate. Note: Do not write to an address that is "(Disabled)". If a "(Disabled)" address is read, an indeterminate value is returned.
22
DS07-12xxx-1E
MB95430H Series
INTERRUPT SOURCE TABLE
Vector table address Interrupt source Interrupt request number Priority order of interrupt Bit name of sources of the interrupt level same level setting register (occurring simultaneously) L00 [1:0] L01 [1:0] L02 [1:0] L03 [1:0] L04 [1:0] L05 [1:0] L06 [1:0] L07 [1:0] L08 [1:0] L09 [1:0] L10 [1:0] L11 [1:0] L12 [1:0] L13 [1:0] L14 [1:0] L15 [1:0] L16 [1:0] L17 [1:0] L18 [1:0] L19 [1:0] L20 [1:0] L21 [1:0] L22 [1:0] L23 [1:0] Low High
Upper
Lower
External interrupt ch. 0 External interrupt ch. 4 External interrupt ch. 1 External interrupt ch. 5 External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 UART/SIO 8/16-bit composite timer ch. 0 (lower) 8/16-bit composite timer ch. 0 (upper) Output compare ch. 0 match Output compare ch. 1 match -- Voltage comparator ch. 0 Voltage comparator ch. 1 Voltage comparator ch. 2 Voltage comparator ch. 3 16-bit free-running timer (compare match/zero-detect/overflow) 16-bit PPG IC -- 8/10-bit A/D converter Time-base timer Watch prescaler -- -- Flash memory
2
IRQ00 IRQ01
FFFAH FFF8H
FFFBH FFF9H
IRQ02 IRQ03 IRQ04 IRQ05 IRQ06 IRQ07 IRQ08 IRQ09 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20 IRQ21 IRQ22 IRQ23
FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H FFD0H FFCEH FFCCH
FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H FFD1H FFCFH FFCDH
DS07-12xxx-1E
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MB95430H Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage*1 Input voltage*1 Output voltage*
1
Symbol VCC VI VO ICLAMP |ICLAMP| IOL1 IOL2
Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 -2 -- -- Max VSS + 6 VSS + 6 VSS + 6 +2 20 15 15
Unit V V V mA mA mA *2 *2
Remarks
Maximum clamp current Total maximum clamp current "L" level maximum output current
Applicable to specific pins*3 Applicable to specific pins*3 Other than P05 and P06 P05 and P06 Other than P05 and P06 Average output current = operating current x operating ratio (1 pin) P05 and P06 Average output current = operating current x operating ratio (1 pin)
IOLAV1 "L" level average current IOLAV2
--
4 mA
--
12
"L" level total maximum output current "L" level total average output current "H" level maximum output current
IOL IOLAV IOH1 IOH2
--
100
mA Total average output current = operating current x operating ratio (Total number of pins) Other than P05 and P06 P05 and P06 Other than P05 and P06 Average output current = operating current x operating ratio (1 pin) P05 and P06 Average output current = operating current x operating ratio (1 pin)
-- -- --
50 -15 -15 -4
mA
mA
IOHAV1 "H" level average current IOHAV2
--
mA -- -8
"H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
IOH IOHAV Pd TA Tstg
--
-100 -50 320 +85 +150
mA Total average output current = operating current x operating ratio (Total number of pins)
-- -- -40 -55
mA mW C C
(Continued)
24
DS07-12xxx-1E
MB95430H Series
(Continued) *1: The parameter is based on VSS = 0.0 V. *2: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating. *3: Applicable to the following pins: P00 to P07, P60 to P67, P70 to P76, PF0 and PF1 * Use under recommended operating conditions. * Use with DC voltage (current). * The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal. * The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current. * When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices. * If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied from the pins, incomplete operations may be executed. * If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. * Do not leave the HV (High Voltage) input pin unconnected. * Example of a recommended circuit * Input/Output equivalent circuit
Protective diode VCC Limiting resistor P-ch N-ch R
HV(High Voltage) input (0 V to 16 V)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-12xxx-1E
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MB95430H Series
2. Recommended Operating Conditions
(VSS = 0.0 V) Parameter Symbol Value Min 2.4*1*2 Power supply voltage VCC 2.3 2.9 2.3 Smoothing capacitor Operating temperature CS TA 0.022 -40 +5 Max 5.5*1 5.5 5.5 5.5 1 +85 +35 V Unit In normal operation In normal operation Hold condition in stop mode F *3 C Other than on-chip debug mode On-chip debug mode Remarks Other than on-chip debug Hold condition in stop mode mode On-chip debug mode
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range. *2: This value becomes 2.88 V when the low-voltage detection reset is used. *3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. * DBG / RST / C pins connection diagram
*
DBG C RST Cs
*: Since the DBG pin becomes a communication pin in on-chip debug mode, set a pull-up resistor value suiting the input/output specifications of P12/EC0/UI/SCL/DBG.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
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DS07-12xxx-1E
MB95430H Series
3. DC Characteristics
(VCC = 5.0 V10%, VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Pin name P03, P04, P12, P65 P00 to P07, P12, P60 to P67, P70 to P76, PF0, PF1, PG1, PG2 PF2 P03, P04, P12, P65 P00 to P07, P12, P60 to P67, P70 to P76, PF0, PF1, PG1, PG2 PF2 P03, P04, P12, P65, PF2 Condition Value Min 0.7 VCC Typ*3 -- Max VCC + 0.3 Unit Remarks When CMOS input level (hysteresis input) is selected
VIHI
*1
V
"H" level input voltage
VIHS
*1
0.8 VCC
--
VCC + 0.3
V
Hysteresis input
VIHM VIL
-- *1
0.7 VCC VSS - 0.3
-- --
VCC + 0.3 0.3 VCC
V V
Hysteresis input When CMOS input level (hysteresis input) is selected
"L" level input voltage
VILS
*1
VSS - 0.3
--
0.2 VCC
V
Hysteresis input
VILM Open-drain output application voltage
--
VSS - 0.3
--
0.3 VCC
V
Hysteresis input P03, P04 and P65 are open-drain output pins when assigned as the SDA/SCL pin of I2C.
VD
--
VSS - 0.3
--
VSS + 5.5
V
"H" level output voltage
VOH1 VOH2
Output pins other than P05, IOH = -4 mA P06, P12 and PF2 P05, P06 IOH = -8 mA Output pins other than P05 IOL = 4 mA and P06 P05, P06 All input pins IOL = 12 mA 0.0 V < VI < VCC
VCC - 0.5 VCC - 0.5 -- -- -5
-- -- -- -- --
-- -- 0.4 0.4 +5
V V V V When pull-up A resistance is disabled When pull-up k resistance is enabled pF (Continued)
"L" level output voltage Input leak current (Hi-Z output leak current) Pull-up resistance Input capacitance
VOL1 VOL2 ILI
RPULL CIN
P00 to P07, PG1, PG2
VI = 0 V
25 --
50 5
100 15
Other than VCC f = 1 MHz and VSS
DS07-12xxx-1E
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MB95430H Series
(VCC = 5.0 V10%, VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Pin name Condition Value Min -- Typ*3 Max 12.1 22 Unit Remarks
Flash memory mA product (except writing and erasing) Flash memory mA product (at writing and erasing) mA At A/D conversion When the voltage mA comparator is operating mA When the OPAMP is operating
ICC
VCC = 5.5 V FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2)
-- -- --
39.3 13.8 12.5
46.8 30.3 23.4
-- VCC = 5.5 V FCH = 32 MHz FMP = 16 MHz Main sleep mode VCC (External clock (divided by 2) operation) VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Subclock mode (divided by 2) TA = +25C VCC = 5.5 V FCL = 32 kHz FMPL = 16 kHz Subsleep mode (divided by 2) TA = +25C VCC = 5.5 V FCL = 32 kHz Watch mode Main stop mode TA = +25C VCC = 5.5 V FCRH = 12.5 MHz FMP = 12.5 MHz Main CR clock mode VCC = 5.5 V Sub-CR clock mode (divided by 2) TA = +25C
13.4
22.3
ICCS
--
5.1
13.2
mA
Power supply current*2
ICCL
--
57
168
A
ICCLS
--
7.6
92
A
ICCT
--
4.2
33
A
ICCMCR VCC ICCSCR
--
9.6
18.2
mA
--
107.4 550
A
(Continued)
28
DS07-12xxx-1E
MB95430H Series
(Continued)
Parameter
Symbol
Pin name
(VCC = 5.0 V10%, VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min Typ*3 Max
ICCTS
ICCH
VCC = 5.5 V FCH = 32 MHz Time-base timer VCC mode (External clock TA = +25C operation) VCC = 5.5 V Substop mode TA = +25C Current consumption for low-voltage detection circuit only Current consumption for the main CR oscillator Current consumption for the sub-CR oscillator oscillating at 100 kHz
--
0.9
3.3
mA
--
3.5
24.8
A
Power supply current*2
ILVD
--
26.9
54
A
ICRH
VCC
--
0.2
0.6
mA
ICRL
--
64.7
72
A
*1: The input levels of P04 can be switched between "CMOS input level" and "hysteresis input level". The input level selection register (ILSR) is used to switch between the two input levels. *2: * The power supply current is determined by the external clock. When the low-voltage detection option is selected, the power-supply current will be the sum of adding the current consumption of the low-voltage detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection option and the CR oscillator are selected, the power supply current will be the sum of adding up the current consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL) and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit are always enabled, and current consumption therefore increases accordingly. * See "4. AC Characteristics: (1) Clock Timing" for FCH and FCL. * See "4. AC Characteristics: (2) Source Clock/Machine Clock" for FMP and FMPL. *3: VCC = 5.0 V, TA = 25C
DS07-12xxx-1E
29
MB95430H Series
4. AC Characteristics
(1) Clock Timing (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Pin name Condition X0, X1 FCH X0 X0, X1 -- X1: open * Value Min 1 1 1 TBD Clock frequency FCRH -- -- TBD TBD TBD -- FCL X0A, X1A -- -- FCRL -- X0, X1 Clock cycle time tHCYL X0 X0, X1 tLCYL Input clock pulse width Input clock rise time and fall time CR oscillation start time tWH1 tWL1 tWH2 tWL2 tCR tCF tCRHWK tCRLWK X0A, X1A X0 X0, X1 X0A X0 X0, X1 -- -- -- -- X1: open * -- X1: open * -- X1: open * -- -- 50 61.5 83.4 30.8 -- 33.4 12.4 -- -- -- -- -- 32.768 100 -- -- -- 30.5 -- -- 15.2 -- -- -- -- -- 200 1000 1000 1000 -- -- -- -- 5 5 80 10 kHz Typ -- -- -- 12.5 10 8 1 32.768 Max Unit Remarks When the main oscillation circuit is used
16.25 MHz 12 32.5 TBD TBD TBD TBD --
MHz When the main external clock is MHz used MHz MHz MHz MHz kHz When the sub-oscillation circuit is used When the sub-external clock is used When the main oscillation circuit is used When the external clock is used When the subclock is used When the external clock is used, the duty ratio should range between 40% and 60%. When the main CR clock is used
kHz When the sub-CR clock is used ns ns ns s ns ns s ns ns s s When the external clock is used When the main CR clock is used When the sub-CR clock is used
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
30
DS07-12xxx-1E
MB95430H Series
tHCYL tWH1 tCR X0, X1 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tCF tWL1
* Figure of main clock input port external connection
When a crystal oscillator or a ceramic oscillator is used When the external clock is used When the external clock (X1 is open) is used
X0
X1 FCH
X0
X1 Open FCH
X0
X1
FCH
tLCYL tWH2 tCR X0A 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tCF tWL2
* Figure of subclock input port external connection
When a crystal oscillator or a ceramic oscillator is used When the external clock is used
X0A
X1A FCL
X0A
X1A Open FCL
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MB95430H Series
(2) Source Clock/Machine Clock (VCC = 5.0 V10%, VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Pin name Value Min 61.5 Typ -- Max 2000 Unit Remarks When the main external clock is used Min: FCH = 32.5 MHz, divided by 2 Max: FCH = 1 MHz, divided by 2 When the main CR clock is used Min: FCRH = 12.5 MHz Max: FCRH = 1 MHz When the sub-oscillation clock is used FCL = 32.768 kHz, divided by 2 When the sub-CR clock is used FCRL = 100 kHz, divided by 2
ns
Source clock cycle time*1
tSCLK
--
80
--
1000
ns
-- -- FSP Source clock frequency FSPL -- 0.5 1 -- --
61 20 -- -- 16.384 50
-- -- 16.25 12.5 -- --
s s
MHz When the main oscillation clock is used MHz When the main CR clock is used kHz When the sub-oscillation clock is used kHz When the sub-CR clock is used FCRL = 100 kHz, divided by 2 When the main oscillation clock is used Min: FSP = 16.25 MHz, no division Max: FSP = 0.5 MHz, divided by 16 When the main CR clock is used Min: FSP = 12.5 MHz Max: FSP = 1 MHz, divided by 16 When the sub-oscillation clock is used Min: FSPL = 16.384 kHz, no division Max: FSPL = 16.384 kHz, divided by 16 When the sub-CR clock is used Min: FSPL = 50 kHz, no division Max: FSPL = 50 kHz, divided by 16
61.5 Machine clock cycle time*2 (minimum instruction execution time)
--
32000
ns
80 tMCLK -- 61
--
16000
ns
--
976.5
s
20 0.031 0.0625 -- FMPL 1.024 3.125
-- -- -- -- --
320 16.25 12.5 16.384 50
s
FMP Machine clock frequency
MHz When the main oscillation clock is used MHz When the main CR clock is used kHz When the sub-oscillation clock is used kHz When the sub-CR clock is used FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock divide ratio select bits (SYCC:DIV1 and DIV0). This source clock is divided to become a machine clock according to the divide ratio set by the machine clock divide ratio select bits (SYCC:DIV1 and DIV0). In addition, a source clock can be selected from the following. * Main clock divided by 2 * Main CR clock * Subclock divided by 2 * Sub-CR clock divided by 2 *2: This is the operating clock of the microcontroller. A machine clock can be selected from the following. * Source clock (no division) * Source clock divided by 4 * Source clock divided by 8 * Source clock divided by 16
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DS07-12xxx-1E
MB95430H Series
* Schematic diagram of the clock generation block
FCH (main oscillation) FCRH (Main CR clock) FCL (sub-oscillation)
Divided by 2
Divided by 2
SCLK (source clock)
FCRL (Sub-CR clock)
Divided by 2
Division circuit x1 x 1/4 x 1/8 x1/16
MCLK (machine clock)
Clock mode select bits (SYCC2: RCS1, RCS0)
Machine clock divide ratio select bits (SYCC:DIV1, DIV0)
* Operating voltage - Operating frequency (When TA = -40C to +85C) MB95430H (without the on-chip debug function)
5.5 5.0
Operating voltage (V)
A/D converter operation range
4.0 3.5 3.0
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
* Operating voltage - Operating frequency (When TA = -40C to +85C) MB95430H (with the on-chip debug function)
5.5 5.0
Operating voltage (V)
A/D converter operation range
4.0 3.5 3.0
2.9
16 kHz
3 MHz
12.5 MHz
16.25 MHz
Source clock frequency (FSP)
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MB95430H Series
(3) External Reset (VCC = 5.0 V10%, VSS = 0.0 V, TA = -40C to +85C) Parameter Symbol Value Min 2 tMCLK*1 RST "L" level pulse width tRSTL Oscillation time of the oscillator*2 + 100 100 *1: See "(2) Source Clock/Machine Clock" for tMCLK. *2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of between hundreds of s and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator clock has an oscillation time of between several s and several ms. * In normal operation
tRSTL RST 0.2 VCC 0.2 VCC
Max -- -- --
Unit ns s s
Remarks In normal operation In stop mode, subclock mode, subsleep mode, watch mode, and power-on In time-base timer mode
* In stop mode, subclock mode, subsleep mode, watch mode and power-on
RST tRSTL 0.2 VCC 90% of amplitude 0.2 VCC
X0
Internal operating clock Oscillation time of oscillator Internal reset
100 s
Oscillation stabilization wait time Execute instruction
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DS07-12xxx-1E
MB95430H Series
(4) Power-on Reset (VSS = 0.0 V, TA = -40C to +85C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Condition -- -- Value Min -- 1 Max 50 -- Unit ms ms Wait time until power-on Remarks
tR 2.5 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as shown below.
VCC Set the slope of rising to a value below 30 mV/ms. Hold condition in stop mode
2.3 V VSS
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35
MB95430H Series
(5) Peripheral Input Timing (VCC = 5.0 V10%, VSS = 0.0 V, TA = -40C to +85C) Parameter Peripheral input "H" pulse width Peripheral input "L" pulse width Symbol tILIH tIHIL Pin name INT00 to INT07, EC0, ADTG, TRG Value Min 2 tMCLK* 2 tMCLK* Max -- -- Unit ns ns
*: See "(2) Source Clock/Machine Clock" for tMCLK.
tILIH tIHIL
INT00 to INT07, EC0, ADTG, TRG
0.8 VCC
0.8 VCC 0.2 VCC 0.2 VCC
36
DS07-12xxx-1E
MB95430H Series
(6) UART/SIO, Serial I/O Timing (VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Min Max UCK UCK, UO UCK, UI UCK, UI UCK UCK UCK, UO UCK, UI UCK, UI External clock operation Internal clock operation 4 tMCLK* -190 2 tMCLK* 2 tMCLK* 4 tMCLK* 4 tMCLK* -- 2 tMCLK* 2 tMCLK* -- +190 -- -- -- -- 190 -- -- ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time UCK UO time Valid UI UCK UCK valid UI hold time Serial clock "H" pulse width Serial clock "L" pulse width UCK UO time Valid UI UCK UCK valid UI hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
*: See "(2) Source Clock/Machine Clock" for tMCLK. * Internal shift clock mode
tSCYC 2.4 V UCK 0.8 V tSLOV 2.4 V UC 0.8 V tIVSH UI 0.2 VCC 0.2 VCC tSHIX 0.8 V
0.8 VCC 0.8 VCC
* External shift clock mode
tSLSH 0.8 VCC UCK 0.2 VCC tSLOV 2.4 V UC 0.8 V tIVSH UI 0.2 VCC 0.2 VCC tSHIX 0.2 VCC tSHSL 0.8 VCC
0.8 VCC 0.8 VCC
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MB95430H Series
(7) Low-voltage Detection (VSS = 0.0 V, TA = -40C to +85C) Parameter Release voltage Detection voltage Hysteresis width Power supply start voltage Power supply end voltage Power supply voltage change time (at power supply rise) Power supply voltage change time (at power supply fall) Reset release delay time Reset detection delay time Symbol VDL+ VDLVHYS Voff Von tr Value Min 2.52 2.42 70 -- 4.9 3000 Typ 2.7 2.6 100 -- -- -- Max 2.88 2.78 -- 2.3 -- -- Unit V V mV V V s Slope of power supply that the reset release signal generates within the rating (VDL+) Slope of power supply that the reset detection signal generates within the rating (VDL-) Remarks At power supply rise At power supply fall
tf td1 td2
300 -- --
-- -- --
-- 300 20
s s s
VCC
Von
Voff
time tf tr
VDL+ VHYS VDL-
Internal reset signal time td2 td1
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DS07-12xxx-1E
MB95430H Series
(8) I2C Timing (VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Parameter Symbol Pin name Condition Standardmode Min SCL clock frequency (Repeated) START condition hold time SDA SCL SCL clock "L" width SCL clock "H" width (Repeated) START condition hold time SCL SDA Data hold time SCL SDA Data setup time SDA SCL STOP condition setup time SCL SDA Bus free time between STOP condition and START condition fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF SCL SCL, SDA SCL SCL SCL, SDA SCL, SDA SCL, SDA SCL, SDA SCL, SDA R = 1.7 k, C = 50 pF*1 0 4.0 4.7 4.0 4.7 0 0.25 4 4.7 Max 100 -- -- -- -- 3.45*2 -- -- -- Fast-mode Unit Min 0 0.6 1.3 0.6 0.6 0 0.1 0.6 1.3 Max 400 -- -- -- -- 0.9*3 -- -- -- kHz s s s s s s s s
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines. *2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the SCL signal at "L" (tLOW) does not extend. *3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT 250ns is fulfilled.
tWAKEUP SDA tLOW SCL tHD;STA tSU;DAT fSCL tSU;STA tSU;STO tHD;DAT tHIGH tHD;STA tBUF
(Continued)
DS07-12xxx-1E
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MB95430H Series
(VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Parameter SCL clock "L" width SCL clock "H" width Sym- Pin Condition bol name tLOW SCL tHIGH SCL Value*2 Min
(2 + nm/2)tMCLK - 20 (nm/2)tMCLK - 20
Max --
(nm/2)tMCLK + 20
Unit ns ns
Remarks Master mode Master mode Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. Master mode
START SCL, condition hold tHD;STA SDA time
(-1 + nm/2)tMCLK - 20
(-1 + nm)tMCLK + 20
ns
STOP condition setup time START condition setup time Bus free time between STOP condition and START condition Data hold time
tSU;STO
SCL, SDA SCL, SDA
(1 + nm/2)tMCLK - 20
(1 + nm/2)tMCLK + 20
ns
tSU;STA
(1 + nm/2)tMCLK - 20
(1 + nm/2)tMCLK + 20
ns
Master mode
tBUF
SCL, SDA
R = 1.7 k, C = 50 pF*1
(2 nm + 4)tMCLK - 20
--
ns
tHD;DAT
SCL, SDA
3 tMCLK - 20
--
ns
Master mode Master mode When assuming that "L" of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Minimum value is applied to interrupt at 9th SCL. Maximum value is applied to the interrupt at the 8th SCL. (Continued)
Data setup time
tSU;DAT
SCL, SDA
(-2 + nm/2)tMCLK - 20
(-1 + nm/2)tMCLK + 20
ns
Setup time between clearing inter- tSU;INT SCL rupt and SCL rising
(nm/2)tMCLK - 20
(1 + nm/2)tMCLK + 20
ns
40
DS07-12xxx-1E
MB95430H Series
(Continued)
Parameter SCL clock "L" width SCL clock "H" width START condition detection STOP condition detection
(VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value*2 Sym- Pin Condition Unit Remarks bol name Min Max tLOW tHIGH tHD;STA SCL SCL SCL, SDA SCL, SDA
4 tMCLK - 20 4 tMCLK - 20 2 tMCLK - 20
-- -- --
ns ns ns
At reception At reception Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception At reception At slave transmission mode At slave transmission mode At reception At reception
tSU;STO
2 tMCLK - 20
--
ns
RESTART condition SCL, tSU;STA detection condition SDA Bus free time Data hold time Data setup time Data hold time Data setup time tBUF tHD;DAT tSU;DAT tHD;DAT tSU;DAT SCL, SDA SCL, SDA SCL, SDA SCL, SDA SCL, SDA R = 1.7 k, C = 50 pF*1
2 tMCLK - 20
--
ns
2 tMCLK - 20 2 tMCLK - 20 tLOW - 3 tMCLK - 20 0 tMCLK - 20 Oscillation stabilization wait time +2 tMCLK - 20
-- -- -- -- --
ns ns ns ns ns
SCL, SDA SCL tWAKEUP SDA (at wakeup function)
--
ns
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines. *2: * * * * See "(2) Source Clock/Machine Clock" for tMCLK. m represents the CS4 bit and CS3 bit (bit 4 and bit 3) in the I2C clock control register (ICCR0). n represents the CS2 bit to CS0 bit (bit 2 to bit 0) in the I2C clock control register (ICCR0). The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the CS4 to CS0 bits in the ICCR0 register. * Standard-mode: m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 10 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 MHz < tMCLK 1 MHz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 MHz < tMCLK 2 MHz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 MHz < tMCLK 4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK 10 MHz * Fast-mode: m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 10 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 MHz < tMCLK 4 MHz (m, n) = (1, 22), (5, 4) : 3.3 MHz < tMCLK 8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK 10 MHz
DS07-12xxx-1E
41
MB95430H Series
(9) Voltage Compare Timing (VCC = 4.0 V to 5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Pin name CMPn_P, CMPn_N (n = 0,1,2,3) CMPn_P, CMPn_N (n = 0,1,2,3) CMPn_O (n = 0,1,2,3) Value Min 0 Typ -- Max VCC - 1.3 Unit Remarks
Voltage range
V
Offset voltage
-10 -- -- --
-- 650 140 --
+10 1210 420 1210
mV ns ns ns 5 mV overdrive 50 mV overdrive Power down recovery PD: 1 0 Power down effective PD: 0 1 Output: "H" level Output stabilization time at power up
Delay time
Power down delay
CMPn_O (n = 0,1,2,3)
0
--
--
ns
Power up stabilization time
CMPn_O (n = 0,1,2,3)
--
--
1210
ns
42
DS07-12xxx-1E
MB95430H Series
(9) Operational Amplifier Timing * Open Loop Configuration (VCC = 4.0 V to 5.5 V, TA = -40C to +85C) Parameter Input voltage range Output voltage range Output resistor load Output capacitor load Offset voltage Open loop bandwidth Open loop gain Power supply rejection ratio Power down recovery time Slew rate Large signal response Small signal response Output stabilization time Pin name OPAMP_P, OPAMP_N OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O Value Min 0.1 0.1 220k -- -- 3 75 60 65 -- 0.3 -- -- -- Typ -- -- -- -- -- -- 85 -- -- -- -- -- -- -- Max 1.5 VCC - 0.1 -- 20 10 -- -- -- -- 200 -- 6 500 60 Unit V V ohm pF mV MHz dB dB dB s V/s s ns s After changes in values of RES0-RES2 AD loading AD loading Minimum driving resistor value AD loading (maximum ESR = 10k) Remarks
Common mode rejection ratio OPAMP_O
DS07-12xxx-1E
43
MB95430H Series
* Closed Loop Configuration (VCC = 4.0 V to 5.5 V, TA = -40C to +85C) Parameter Pin name Value Min -- -- -- 0.1 -- 1 10 -- -- -- 0.3 -- -- -- Typ 0.07 0.07 -- -- -- -- -- -- -- -- -- -- -- -- Max 0.09 0.10 VCC/Gain VCC - 0.1 20 -- 60 10% 15% 200 -- 6 500 60 Unit V V V V pF AD loading (maximum ESR = 10k) Remarks
Minimum input voltage range OPAMP_P, (10x, 20x, 60x) OPAMP_N Minimum input voltage range OPAMP_P, (30x, 40x, 50x) OPAMP_N Maximum input voltage range OPAMP_P, (10x, 20x, 30x, 40x, 50x, 60x) OPAMP_N Output voltage range Output capacitor load Closed loop bandwidth Closed loop gain Closed loop gain error* (10x, 20x, 30x, 40x, 50x) Closed loop gain error* (60x) Power down recovery time Slew rate Large signal response Small signal response Output stabilization time OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O OPAMP_O
MHz AD loading V/V Selectable -- -- s V/s s ns s After changes in values of RES0-RES2
*: Gain error = 1 - (actual gain / design gain)
44
DS07-12xxx-1E
MB95430H Series
5. A/D Converter (1) A/D Converter Electrical Characteristics
(VCC = 4.0 V to 5.5 V, VSS = 0.0 V, TA = -40C to +85C) Parameter Resolution Total error Linearity error Differential linear error Zero transition voltage Full-scale transition voltage Compare time VOT VFST -- -- Symbol Value Min -- -3 -2.5 -1.9 Typ -- -- -- -- Max 10 +3 +2.5 +1.9 Unit bit LSB LSB LSB V V s s s 4.5 V VCC 5.5 V 4.0 V VCC < 4.5 V 4.5 V VCC 5.5 V, with external impedance < 5.4 k 4.0 V VCC < 4.5 V, with external impedance < 2.4 k Remarks
VSS - 1.5 LSB VSS + 0.5 LSB VSS + 2.5 LSB VCC - 4.5 LSB 0.9 1.8 0.6 VCC - 2 LSB -- -- -- VCC + 0.5 LSB 16500 16500
Sampling time
-- 1.2 -- -- -- +0.3 VCC s A V
Analog input current Analog input voltage
IAIN VAIN
-0.3 VSS
DS07-12xxx-1E
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MB95430H Series
(2) Notes on Using the A/D Converter * External impedance of analog input and its sampling time * The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 F to the analog input pin. * Analog input equivalent circuit
Analog input R C
Comparator
During sampling: ON
VCC 4.5 V VCC 5.5 V 4.0 V VCC < 4.5 V R 1.95 k (Max) 8.98 k (Max) C 17 pF (Max) 17 pF (Max)
Note: The values are reference values.
* Relationship between external impedance and minimum sampling time
[External impedance = 0 k to 100 k]
100 20
[External impedance = 0 k to 20 k] External impedance [k]
18 16 14 12 10 8 6 4 2 0
External impedance [k]
90 80 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 14
(VCC 4.5 V) (VCC 4.0 V)
(VCC 4.5 V) (VCC 4.0 V)
0
1
2
3
4
Minimum sampling time [s]
Minimum sampling time [s]
* A/D conversion error As |VCC-VSS| decreases, the A/D conversion error increases proportionately.
46
DS07-12xxx-1E
MB95430H Series
(3) Definitions of A/D Converter Terms * Resolution It indicates the level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. * Linearity error (unit: LSB) It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") of a device to the full-scale transition point ("11 1111 1111" "11 1111 1110") of the same device. * Differential linear error (unit: LSB) It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value. * Total error (unit: LSB) It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
3FFH 3FEH 3FDH 2 LSB
Total error
3FFH 3FEH 3FDH Actual conversion characteristic
{1 LSB x (N-1) + 0.5 LSB}
VFST
Digital output
Digital output
004H 003H 002H 001H 0.5 LSB
004H 003H
VOT
1 LSB
VNT
Actual conversion characteristic Ideal characteristic
002H 001H
VSS
Analog input 1 LSB = VCC - VSS (V) 1024
VCC
VSS
Analog input
VCC
VNT - {1 LSB x (N - 1) + 0.5 LSB} Total error of = [LSB] digital output N 1 LSB
N
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
(Continued)
DS07-12xxx-1E
47
MB95430H Series
(Continued)
Zero transition error
004H Actual conversion characteristic 003H 3FFH Actual conversion characteristic
Full-scale transition error
Ideal characteristic
Digital output
Digital output
3FEH
002H Ideal characteristic 001H
VFST
3FDH (measurement value) Actual conversion characteristic
Actual conversion characteristic
VOT (measurement value) VSS Analog input VCC
3FCH
VSS
Analog input
VCC
Linearity error
3FFH 3FEH 3FDH Actual conversion characteristic
Differential linearity error
Ideal characteristic (N+1)H Actual conversion characteristic
{1 LSB x N + VOT} Digital output VFST
(measurement value) NH
V(N+1)T
Digital output
VNT
004H 003H 002H 001H Actual conversion characteristic Ideal characteristic
(N-1)H
VNT
Actual conversion characteristic
(N-2)H
VOT (measurement value) VSS Analog input VCC VSS Analog input VCC
VNT - {1 LSB x N + VOT} Linearity error = of digital output N 1 LSB
V(N+1)T - VNT Differential linear error = -1 of digital output N 1 LSB
N
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH VOT (ideal value) = VSS + 0.5 LSB [V] VFST (ideal value) = VCC - 2 LSB [V]
48
DS07-12xxx-1E
MB95430H Series
6. Flash Memory Write/Erase Characteristics
Parameter Sector erase time (2 Kbyte sector) Sector erase time (16 Kbyte sector) Byte writing time Erase/write cycle Power supply voltage at erase/ write Flash memory data retention time Value Min -- -- -- 100000 3.0 20*3 Typ 0.2*1 0.5*1 21 -- -- -- Max 0.5*2 7.5*2 6100*2 -- 5.5 -- Unit s s s cycle V year Average TA = +85C Remarks The time of writing 00H prior to erasure is excluded. The time of writing 00H prior to erasure is excluded. System-level overhead is excluded.
*1: TA = +25C, VCC = 5.0 V, 100000 cycles *2: TA = +85C, VCC = 3.0 V, 100000 cycles *3: This value is converted from the result of a technology reliability assessment. (The value is converted from the result of a high temperature accelerated test using the Arrhenius equation with the average temperature being +85C).
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MB95430H Series
MASK OPTIONS
Part Number Selectable/Fixed 1 2 Reset With dedicated reset input MB95F432H MB95F433H MB95F434H Fixed Without dedicated reset input MB95F432K MB95F433K MB95F434K
No.
Low-voltage detection reset Without low-voltage detection reset With low-voltage detection reset
50
DS07-12xxx-1E
MB95430H Series
ORDERING INFORMATION
Part Number MB95F432HPMC-G-SNE2 MB95F432KPMC-G-SNE2 MB95F433HPMC-G-SNE2 MB95F433KPMC-G-SNE2 MB95F434HPMC-G-SNE2 MB95F434KPMC-G-SNE2 MB95F432HP-G-SH-SNE2 MB95F432KP-G-SH-SNE2 MB95F433HP-G-SH-SNE2 MB95F433KP-G-SH-SNE2 MB95F434HP-G-SH-SNE2 MB95F434KP-G-SH-SNE2 Package
32-pin plastic LQFP (FPT-32P-M30)
32-pin plastic SH-DIP (DIP-32P-M06)
DS07-12xxx-1E
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MB95430H Series
PACKAGE DIMENSION
32-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height 0.80 mm 7.00 mm x 7.00 mm Gullwing Plastic mold 1.60 mm MAX
(FPT-32P-M30)
32-pin plastic LQFP (FPT-32P-M30)
9.000.20(.354.008)SQ
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
+0.05 +.002
* 7.000.10(.276.004)SQ
24 17
0.13 -0.00 .005 -.000
25
16
0.10(.004)
Details of "A" part
INDEX
1.60 MAX (Mounting height) (.063) MAX
0.25(.010)
32
9
0~7
1
8
"A"
0.80(.031)
0.35 -0.03
+0.08 +.003
0.600.15 (.024.006)
0.100.05 (.004.002)
.014 -.001
0.20(.008)
M
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F32051S-c-1-2
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued)
52
DS07-12xxx-1E
MB95430H Series
(Continued)
32-pin plastic SDIP Lead pitch Low space Sealing method 1.778 mm 10.16 mm Plastic mold
(DIP-32P-M06)
32-pin plastic SDIP (DIP-32P-M06)
*28.00 -0.30 1.102
+0.20 +.008 -.012
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness.
INDEX *8.890.25 (.350.010)
1.02 .040 4.70 -0.20
+0.70 +.028
+0.30 -0.20 +.012 -.008
.185 -.008
0.51(.020) MIN.
3.30
.130 -.012
+0.20 -0.30 +.008
0.27 -0.07 1.27(.050) MAX. 1.778(.070) 0.48 -0.12 .019 -.005
+.003 +0.08
+0.03 +.001
.011-.003 0.25(.010)
M
10.16(.400) 0~15
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED D32018S-c-1-3
Dimensions in mm (inches). Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/
DS07-12xxx-1E
53
MB95430H Series
MEMO
54
DS07-12xxx-1E
MB95430H Series
MEMO
DS07-12xxx-1E
55
MB95430H Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department

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